A typical SRAM is designed to store many thousands of bits of information. These bits are stored in individual cells, organized in rows and columns to make efficient use of space on a semiconductor substrate containing the SRAM device. A commonly used cell architecture is known as the “6T” cell, by virtue of having six MOS transistors. Four transistors defining an SRAM cell core or memory element are configured as cross-coupled CMOS inverters, which act as a bistable circuit that indefinitely holds the state imposed onto it while powered. Each CMOS inverter includes a load or “pull-up” transistor and a driver or “pull-down” transistor. The output of the two inverters will be in opposite states, except during transitions from one state to another. Two additional transistors are known as “pass gate” transistors, which provide access to the cross-coupled inverters during a read operation (herein referred to as READ) or write operation (herein referred to as WRITE). The gate inputs of the pass transistors are typically connected in common to a “word line”. The drain of one pass gate transistor is connected to a “bit line”, while the drain of the other pass gate transistor is connected to the logical complement of the bit line. Although present memory systems provide acceptable performance, further improvements that provide more stable operating characteristics would be beneficial in the art.